The present invention relates to the field of digital computers and, in particular, to apparatus and methods for processing instructions in high speed data processing systems.
Data processing systems generally include a central processor, an associated storage system (or main memory), and peripheral devices and associated interfaces. Typically, the main memory consists of relatively low cost, high-capacity digital storage devices. The peripheral devices may be, for example, non-volatile semi-permanent storage media, such as magnetic disks and magnetic tape drives. In order to carry out tasks, the central processor of such systems executes a succession of instructions which operate on data. The succession of instructions and the data those instructions reference are referred to as a program.
In operation of such systems, programs are initially brought to an intermediate storage area, usually in the main memory. The central processor may then interface directly to the main memory to execute the stored program. However, this procedure places limitations on performance due principally to the relatively long times required in accessing that main memory. To overcome these limitations a high speed (i.e. relatively fast access) storage system, in some cases called a cache, is used for holding currently used portions of programs within the central processor itself. The cache interfaces with main memory through memory control hardware which handles program transfers between the central processor, main memory and the peripheral device interfaces.
One form of computer, typically a "mainframe" computer has been developed in the prior art to concurrently hardware process a succession of instructions in a so-called "pipeline" processor. In such pipeline processors each instruction is executed in part at each of a succession of stages. After the instruction has been processed at each of the stages, the execution is complete. With this configuration, as an instruction is passed from one stage to the next, that instruction is replaced by the next instruction in the program. Thus, the stages together form a "pipeline" which, at any given time, is executing, in part, a succession of instructions. Such instruction pipelines for processing a plurality of instructions in parallel are found in several mainframe computers. These processors consist of single pipelines of varying length and employ hardwired logic for all data manipulation. The large quantity of control logic in such machines makes them extremely fast, but also very expensive.
Another form of computer system, typically a "minicomputer," incorporates microcode control of instruction execution. Generally, under microcode control, each instruction is fully executed before execution of the next instruction begins. Microcode-controlled execution does not provide as high performance (principally in terms of speed) as hardwired control, but the microcode control does permit significant cost advantages compared to hardwired systems. As a result, microcode control of instruction execution has been employed in many cost-sensitive machines. Microcode reduces the total quantity of hardware in the processor and also allows much more flexibility in terms of adapting to changes which may be required during system operation. Unfortunately, the conventional pipeline techniques for instruction execution are not compatible with the multiple steps which must be performed to execute some instructions in a microcode-controlled environment.
Accordingly, it is an object of the present invention to provide an improved computer system.
Another object is to provide performance characteristics heretofore associated only with mainframes while maintaining a cost profile consistent with the minicomputers.
It is yet another object to provide a computer system incorporating pipelined instruction processing and microcode-controlled instruction execution.